/* the head file modifier:     g   2014-12-04 15:19:49*/

/*  
* Copyright (C) 2013 Spreadtrum Communications Inc.  
*
* This program is free software; you can redistribute it and/or  
* modify it under the terms of the GNU General Public License 
* as published by the Free Software Foundation; either version 2 
* of the License, or (at your option) any later version.  
* 
* This program is distributed in the hope that it will be useful, 
* but WITHOUT ANY WARRANTY; without even the implied warranty of 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
* GNU General Public License for more details.  
* 
*************************************************  
* Automatically generated C header: do not edit *  
*************************************************  
*/  
#ifndef __H_REGS_PMU_APB_HEADFILE_H__
#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__

#define  REGS_PMU_APB

/* registers definitions for PMU_APB */
#define REG_PMU_APB_PD_CA53_TOP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA53_TOP_CFG*/
#define REG_PMU_APB_PD_CA53_LIT_MP4_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA53_LIT_MP4_CFG*/
#define REG_PMU_APB_PD_CA53_LIT_C0_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA53_LIT_C0_CFG*/
#define REG_PMU_APB_PD_CA53_LIT_C1_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA53_LIT_C1_CFG*/
#define REG_PMU_APB_PD_CA53_LIT_C2_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_CA53_LIT_C2_CFG*/
#define REG_PMU_APB_PD_CA53_LIT_C3_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_CA53_LIT_C3_CFG*/
#define REG_PMU_APB_PD_CA53_BIG_MP4_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_CA53_BIG_MP4_CFG*/
#define REG_PMU_APB_PD_CA53_BIG_C0_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_CA53_BIG_C0_CFG*/
#define REG_PMU_APB_PD_CA53_BIG_C1_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CA53_BIG_C1_CFG*/
#define REG_PMU_APB_PD_CA53_BIG_C2_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CA53_BIG_C2_CFG*/
#define REG_PMU_APB_PD_CA53_BIG_C3_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CA53_BIG_C3_CFG*/
#define REG_PMU_APB_PD_AP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_AP_SYS_CFG*/
#define REG_PMU_APB_PD_VSP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_VSP_SYS_CFG*/
#define REG_PMU_APB_PD_DBG_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_DBG_SYS_CFG*/
#define REG_PMU_APB_PD_CAM_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CAM_SYS_CFG*/
#define REG_PMU_APB_PD_DISP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)/*PD_DISP_SYS_CFG*/
#define REG_PMU_APB_PD_GPU_TOP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_GPU_TOP_CFG*/
#define REG_PMU_APB_PD_GPU_C0_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_GPU_C0_CFG*/
#define REG_PMU_APB_PD_GPU_C1_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_GPU_C1_CFG*/
#define REG_PMU_APB_PD_PUB0_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_PUB0_SYS_CFG*/
#define REG_PMU_APB_PD_PUB1_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_PUB1_SYS_CFG*/
#define REG_PMU_APB_PD_WTLCP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_WTLCP_SYS_CFG*/
#define REG_PMU_APB_PD_WTLCP_TGDSP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_WTLCP_TGDSP_CFG*/
#define REG_PMU_APB_PD_WTLCP_LDSP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*PD_WTLCP_LDSP_CFG*/
#define REG_PMU_APB_PD_WTLCP_HU3GE_A_CFG		SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*PD_WTLCP_HU3GE_A_CFG*/
#define REG_PMU_APB_PD_WTLCP_GSM_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_WTLCP_GSM_CFG*/
#define REG_PMU_APB_PD_WTLCP_TD_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)/*PD_WTLCP_TD_CFG*/
#define REG_PMU_APB_PD_WTLCP_LTE_P1_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*PD_WTLCP_LTE_P1_CFG*/
#define REG_PMU_APB_PD_WTLCP_LTE_P2_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*PD_WTLCP_LTE_P2_CFG*/
#define REG_PMU_APB_PD_AGCP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PD_AGCP_SYS_CFG*/
#define REG_PMU_APB_PD_AGCP_DSP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PD_AGCP_DSP_CFG*/
#define REG_PMU_APB_PD_AGCP_GSM_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*PD_AGCP_GSM_CFG*/
#define REG_PMU_APB_PD_PUBCP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*PD_PUBCP_SYS_CFG*/
#define REG_PMU_APB_RC_WAIT_CNT				SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*RC_WAIT_CNT*/
#define REG_PMU_APB_XTL_WAIT_CNT			SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTL_WAIT_CNT*/
#define REG_PMU_APB_XTLBUF_WAIT_CNT			SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF_WAIT_CNT*/
#define REG_PMU_APB_PLL_WAIT_CNT1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*PLL_WAIT_CNT1*/
#define REG_PMU_APB_PLL_WAIT_CNT2			SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*PLL_WAIT_CNT2*/
#define REG_PMU_APB_PLL_WAIT_CNT3			SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*PLL_WAIT_CNT3*/
#define REG_PMU_APB_AP_LP_AUTO_CTRL			SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*AP_LP_AUTO_CTRL*/
#define REG_PMU_APB_XTLBUF0_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*XTLBUF0_REL_CFG*/
#define REG_PMU_APB_XTL0_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*XTL0_REL_CFG*/
#define REG_PMU_APB_MPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*MPLL_REL_CFG*/
#define REG_PMU_APB_DPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*DPLL_REL_CFG*/
#define REG_PMU_APB_LTEPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)/*LTEPLL_REL_CFG*/
#define REG_PMU_APB_TWPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*TWPLL_REL_CFG*/
#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*LVDSDIS_PLL_REL_CFG*/
#define REG_PMU_APB_SYS_SOFT_RST			SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*SYS_SOFT_RST*/
#define REG_PMU_APB_PUBCP_SLP_STATUS_DBG0		SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PUBCP_SLP_STATUS_DBG0*/
#define REG_PMU_APB_WTLCP_SLP_STATUS_DBG0		SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*WTLCP_SLP_STATUS_DBG0*/
#define REG_PMU_APB_AGCP_SLP_STATUS_DBG0		SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*AGCP_SLP_STATUS_DBG0*/
#define REG_PMU_APB_PWR_STATUS0_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*PWR_STATUS0_DBG*/
#define REG_PMU_APB_PWR_STATUS1_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)/*PWR_STATUS1_DBG*/
#define REG_PMU_APB_PWR_STATUS2_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)/*PWR_STATUS2_DBG*/
#define REG_PMU_APB_PWR_STATUS3_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)/*PWR_STATUS3_DBG*/
#define REG_PMU_APB_PWR_STATUS4_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)/*PWR_STATUS4_DBG*/
#define REG_PMU_APB_SLEEP_CTRL				SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)/*SLEEP_CTRL*/
#define REG_PMU_APB_DDR_SLEEP_CTRL			SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)/*DDR_SLEEP_CTRL*/
#define REG_PMU_APB_SLEEP_STATUS			SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)/*SLEEP_STATUS*/
#define REG_PMU_APB_DDR0_CHN_SLEEP_CTRL0		SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)/*DDR0_CHN_SLEEP_CTRL0*/
#define REG_PMU_APB_DDR1_CHN_SLEEP_CTRL0		SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR1_CHN_SLEEP_CTRL0*/
#define REG_PMU_APB_PD_WTLCP_LTE_P3_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*PD_WTLCP_LTE_P3_CFG*/
#define REG_PMU_APB_PD_WTLCP_LTE_P4_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00100)/*PD_WTLCP_LTE_P4_CFG*/
#define REG_PMU_APB_XTLBUF1_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00104)/*XTLBUF1_REL_CFG*/
#define REG_PMU_APB_XTLBUF2_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00108)/*XTLBUF2_REL_CFG*/
#define REG_PMU_APB_LTEPLL1_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0010C)/*LTEPLL1_REL_CFG*/
#define REG_PMU_APB_26M_SEL_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*26M_SEL_CFG*/
#define REG_PMU_APB_BISR_DONE_STATUS1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)/*BISR_DONE_STATUS1*/
#define REG_PMU_APB_BISR_BUSY_STATUS1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)/*BISR_BUSY_STATUS1*/
#define REG_PMU_APB_BISR_BYP_CFG1			SCI_ADDR(REGS_PMU_APB_BASE, 0x011c)/*BISR_BYP_CFG1*/
#define REG_PMU_APB_BISR_EN_CFG1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)/*BISR_EN_CFG1*/
#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0		SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)/*CGM_AUTO_GATE_SEL_CFG0*/
#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1		SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)/*CGM_AUTO_GATE_SEL_CFG1*/
#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2		SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*CGM_AUTO_GATE_SEL_CFG2*/
#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3		SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*CGM_AUTO_GATE_SEL_CFG3*/
#define REG_PMU_APB_CGM_FORCE_EN_CFG0			SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*CGM_FORCE_EN_CFG0*/
#define REG_PMU_APB_CGM_FORCE_EN_CFG1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*CGM_FORCE_EN_CFG1*/
#define REG_PMU_APB_CGM_FORCE_EN_CFG2			SCI_ADDR(REGS_PMU_APB_BASE, 0x013c)/*CGM_FORCE_EN_CFG2*/
#define REG_PMU_APB_CGM_FORCE_EN_CFG3			SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*CGM_FORCE_EN_CFG3*/
#define REG_PMU_APB_SLEEP_XTLON_CTRL			SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*SLEEP_XTLON_CTRL*/
#define REG_PMU_APB_PD_WTLCP_HU3GE_B_CFG		SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*PD_WTLCP_HU3GE_B_CFG*/
#define REG_PMU_APB_MEM_SLP_CFG0			SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*MEM_SLP_CFG0*/
#define REG_PMU_APB_MEM_SD_CFG0				SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*MEM_SD_CFG*/
#define REG_PMU_APB_MEM_AUTO_SLP_EN			SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*MEM_AUTO_SLP_EN*/
#define REG_PMU_APB_MEM_AUTO_SD_EN			SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*MEM_AUTO_SD_EN*/
#define REG_PMU_APB_BISR_DONE_STATUS2			SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*BISR_DONE_STATUS2*/
#define REG_PMU_APB_BISR_BUSY_STATUS2			SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)/*BISR_BUSY_STATUS2*/
#define REG_PMU_APB_BISR_BYP_CFG2			SCI_ADDR(REGS_PMU_APB_BASE, 0x0164)/*BISR_BYP_CFG2*/
#define REG_PMU_APB_BISR_EN_CFG2			SCI_ADDR(REGS_PMU_APB_BASE, 0x0168)/*BISR_EN_CFG2*/
#define REG_PMU_APB_RPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x016C)/*RPLL_REL_CFG*/
#define REG_PMU_APB_PWR_CNT_WAIT_CFG0			SCI_ADDR(REGS_PMU_APB_BASE, 0x0170)/*PWR_CNT_WAIT_CFG0*/
#define REG_PMU_APB_PWR_CNT_WAIT_CFG1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0174)/*PWR_CNT_WAIT_CFG1*/
#define REG_PMU_APB_RC_REL_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x0178)/*RC_REL_CFG*/
#define REG_PMU_APB_DDR_SLEEP_DISABLE_ACK_BYP		SCI_ADDR(REGS_PMU_APB_BASE, 0x017C)/*DDR_SLEEP_DISABLE_ACK_BYP*/
#define REG_PMU_APB_GLB_SLEEP_ENABLE			SCI_ADDR(REGS_PMU_APB_BASE, 0x0180)/*GLB_SLEEP_ENABLE*/
#define REG_PMU_APB_DDR_SLEEP_DISABLE_ACK		SCI_ADDR(REGS_PMU_APB_BASE, 0x0184)/*DDR_SLEEP_DISABLE_ACK*/
#define REG_PMU_APB_DDR_SLEEP_DISABLE			SCI_ADDR(REGS_PMU_APB_BASE, 0x0188)/*DDR_SLEEP_DISABLE*/
#define REG_PMU_APB_PUB_FORCE_SLEEP			SCI_ADDR(REGS_PMU_APB_BASE, 0x018C)/*PUB_FORCE_SLEEP*/
#define REG_PMU_APB_NOC_SLEEP_STOP_BYP			SCI_ADDR(REGS_PMU_APB_BASE, 0x0190)/*NOC_SLEEP_STOP_BYP*/
#define REG_PMU_APB_NOC_SLEEP_STOP_STATUS		SCI_ADDR(REGS_PMU_APB_BASE, 0x0194)/*NOC_SLEEP_STOP_STATUS*/
#define REG_PMU_APB_AGCP_DSP_CORE_INT_DISABLE		SCI_ADDR(REGS_PMU_APB_BASE, 0x0198)/*AGCP_DSP_CORE_INT_DISABLE*/
#define REG_PMU_APB_WTLCP_TGDSP_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x019C)/*WTLCP_TGDSP_CORE_INT_DISABLE*/
#define REG_PMU_APB_WTLCP_LDSP_CORE_INT_DISABLE		SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0)/*WTLCP_LDSP_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_LIT_C0_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01A4)/*CA53_LIT_C0_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_LIT_C1_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01A8)/*CA53_LIT_C1_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_LIT_C2_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01AC)/*CA53_LIT_C2_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_LIT_C3_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01B0)/*CA53_LIT_C3_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_BIG_C0_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01B4)/*CA53_BIG_C0_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_BIG_C1_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01B8)/*CA53_BIG_C1_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_BIG_C2_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01BC)/*CA53_BIG_C2_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_BIG_C3_CORE_INT_DISABLE	SCI_ADDR(REGS_PMU_APB_BASE, 0x01C0)/*CA53_BIG_C3_CORE_INT_DISABLE*/
#define REG_PMU_APB_PUBCP_CR5_CORE_INT_DISABLE		SCI_ADDR(REGS_PMU_APB_BASE, 0x01C4)/*PUBCP_CR5_CORE_INT_DISABLE*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC0		SCI_ADDR(REGS_PMU_APB_BASE, 0x01C8)/*CA53_WAKEUP_IRQ_TEST_SRC0*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SEL		SCI_ADDR(REGS_PMU_APB_BASE, 0x01CC)/*CA53_WAKEUP_IRQ_TEST_SEL*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC1		SCI_ADDR(REGS_PMU_APB_BASE, 0x01DC)/*CA53_WAKEUP_IRQ_TEST_SRC1*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC2		SCI_ADDR(REGS_PMU_APB_BASE, 0x01E0)/*CA53_WAKEUP_IRQ_TEST_SRC2*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC3		SCI_ADDR(REGS_PMU_APB_BASE, 0x01E8)/*CA53_WAKEUP_IRQ_TEST_SRC3*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC4		SCI_ADDR(REGS_PMU_APB_BASE, 0x01F0)/*CA53_WAKEUP_IRQ_TEST_SRC4*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC5		SCI_ADDR(REGS_PMU_APB_BASE, 0x01F8)/*CA53_WAKEUP_IRQ_TEST_SRC5*/
#define REG_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_TEST_SRC	SCI_ADDR(REGS_PMU_APB_BASE, 0x0200)/*WTLCP_TGDSP_WAKEUP_IRQ_TEST_SRC*/
#define REG_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_TEST_SEL	SCI_ADDR(REGS_PMU_APB_BASE, 0x0204)/*WTLCP_TGDSP_WAKEUP_IRQ_TEST_SEL*/
#define REG_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_TEST_SRC	SCI_ADDR(REGS_PMU_APB_BASE, 0x0208)/*WTLCP_LDSP_WAKEUP_IRQ_TEST_SRC*/
#define REG_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_TEST_SEL	SCI_ADDR(REGS_PMU_APB_BASE, 0x020C)/*WTLCP_LDSP_WAKEUP_IRQ_TEST_SEL*/
#define REG_PMU_APB_AGCP_DSP_WAKEUP_IRQ_TEST_SRC	SCI_ADDR(REGS_PMU_APB_BASE, 0x0210)/*AGCP_DSP_WAKEUP_IRQ_TEST_SRC*/
#define REG_PMU_APB_AGCP_DSP_WAKEUP_IRQ_TEST_SEL	SCI_ADDR(REGS_PMU_APB_BASE, 0x0214)/*AGCP_DSP_WAKEUP_IRQ_TEST_SEL*/
#define REG_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_TEST_SRC	SCI_ADDR(REGS_PMU_APB_BASE, 0x0218)/*PUBCP_CR5_WAKEUP_IRQ_TEST_SRC*/
#define REG_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_TEST_SEL	SCI_ADDR(REGS_PMU_APB_BASE, 0x021C)/*PUBCP_CR5_WAKEUP_IRQ_TEST_SEL*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_EN0			SCI_ADDR(REGS_PMU_APB_BASE, 0x0220)/*CA53_WAKEUP_IRQ_EN0*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_EN1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0224)/*CA53_WAKEUP_IRQ_EN1*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_EN2			SCI_ADDR(REGS_PMU_APB_BASE, 0x0228)/*CA53_WAKEUP_IRQ_EN2*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_EN3			SCI_ADDR(REGS_PMU_APB_BASE, 0x022C)/*CA53_WAKEUP_IRQ_EN3*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_EN4			SCI_ADDR(REGS_PMU_APB_BASE, 0x0230)/*CA53_WAKEUP_IRQ_EN4*/
#define REG_PMU_APB_CA53_WAKEUP_IRQ_EN5			SCI_ADDR(REGS_PMU_APB_BASE, 0x0234)/*CA53_WAKEUP_IRQ_EN5*/
#define REG_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x0238)/*WTLCP_TGDSP_WAKEUP_IRQ_EN*/
#define REG_PMU_APB_AGCP_DSP_WAKEUP_IRQ_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x023C)/*AGCP_DSP_WAKEUP_IRQ_EN*/
#define REG_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x0240)/*PUBCP_CR5_WAKEUP_IRQ_EN*/
#define REG_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x025C)/*WTLCP_LDSP_WAKEUP_IRQ_EN*/
#define REG_PMU_APB_CM3_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x0260)/*CM3_DSLP_ENA*/
#define REG_PMU_APB_CA53_BIG_C3_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0264)/*CA53_BIG_C3_DSLP_ENA*/
#define REG_PMU_APB_CA53_BIG_C2_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0268)/*CA53_BIG_C2_DSLP_ENA*/
#define REG_PMU_APB_CA53_BIG_C1_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x026C)/*CA53_BIG_C1_DSLP_ENA*/
#define REG_PMU_APB_CA53_BIG_C0_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0270)/*CA53_BIG_C0_DSLP_ENA*/
#define REG_PMU_APB_CA53_LIT_C3_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0274)/*CA53_LIT_C3_DSLP_ENA*/
#define REG_PMU_APB_CA53_LIT_C2_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0278)/*CA53_LIT_C2_DSLP_ENA*/
#define REG_PMU_APB_CA53_LIT_C1_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x027C)/*CA53_LIT_C1_DSLP_ENA*/
#define REG_PMU_APB_CA53_LIT_C0_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0280)/*CA53_LIT_C0_DSLP_ENA*/
#define REG_PMU_APB_WTLCP_TGDSP_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0284)/*WTLCP_TGDSP_DSLP_ENA*/
#define REG_PMU_APB_WTLCP_LDSP_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x0288)/*WTLCP_LDSP_DSLP_ENA*/
#define REG_PMU_APB_AGCP_DSP_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x028C)/*AGCP_DSP_DSLP_ENA*/
#define REG_PMU_APB_CA53_BIG_MP4_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0290)/*CA53_BIG_MP4_DSLP_ENA*/
#define REG_PMU_APB_CA53_LIT_MP4_DSLP_ENA		SCI_ADDR(REGS_PMU_APB_BASE, 0x0294)/*CA53_LIT_MP4_DSLP_ENA*/
#define REG_PMU_APB_CA53_TOP_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x0298)/*CA53_TOP_DSLP_ENA*/
#define REG_PMU_APB_AP_DSLP_ENA				SCI_ADDR(REGS_PMU_APB_BASE, 0x029C)/*AP_DSLP_ENA*/
#define REG_PMU_APB_PUBCP_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x02A0)/*PUBCP_DSLP_ENA*/
#define REG_PMU_APB_WTLCP_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x02A4)/*WTLCP_DSLP_ENA*/
#define REG_PMU_APB_AGCP_DSLP_ENA			SCI_ADDR(REGS_PMU_APB_BASE, 0x02A8)/*AGCP_DSLP_ENA*/
#define REG_PMU_APB_USB_PMU				SCI_ADDR(REGS_PMU_APB_BASE, 0x02AC)/*USB_PMU*/
#define REG_PMU_APB_PWR_STATUS6_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x02B0)/*PWR_STATUS6_DBG*/
#define REG_PMU_APB_PWR_ST_DEBUG_DLY0			SCI_ADDR(REGS_PMU_APB_BASE, 0x0300)/*PWR_ST_DEBUG_DLY0*/
#define REG_PMU_APB_PWR_ST_DEBUG_DLY1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0304)/*PWR_ST_DEBUG_DLY1*/
#define REG_PMU_APB_LIGHT_SLEEP_ENABLE			SCI_ADDR(REGS_PMU_APB_BASE, 0x0308)/*LIGHT_SLEEP_ENABLE*/
#define REG_PMU_APB_PAD_OUT_ADIE_CTRL0			SCI_ADDR(REGS_PMU_APB_BASE, 0x030C)/*PAD_OUT_ADIE_CTRL0*/
#define REG_PMU_APB_DDR_PHY_DATA_FRC_RET		SCI_ADDR(REGS_PMU_APB_BASE, 0x0310)/*DDR_PHY_DATA_FRC_RET*/
#define REG_PMU_APB_PLL_CNT_DONE_STATUS			SCI_ADDR(REGS_PMU_APB_BASE, 0x0314)/*PLL_CNT_DONE_STATUS*/
#define REG_PMU_APB_POWER_SWITCH_ACK_D_STATUS0		SCI_ADDR(REGS_PMU_APB_BASE, 0x0318)/*POWER_SWITCH_ACK_D_STATUS0*/
#define REG_PMU_APB_POWER_SWITCH_ACK_M_STATUS0		SCI_ADDR(REGS_PMU_APB_BASE, 0x031C)/*POWER_SWITCH_ACK_M_STATUS0*/
#define REG_PMU_APB_POWER_SWITCH_ACK_D_STATUS1		SCI_ADDR(REGS_PMU_APB_BASE, 0x0320)/*POWER_SWITCH_ACK_D_STATUS1*/
#define REG_PMU_APB_POWER_SWITCH_ACK_M_STATUS1		SCI_ADDR(REGS_PMU_APB_BASE, 0x0324)/*POWER_SWITCH_ACK_M_STATUS1*/
#define REG_PMU_APB_CGM_PMU_SEL				SCI_ADDR(REGS_PMU_APB_BASE, 0x0328)/*CGM_PMU_SEL*/
#define REG_PMU_APB_GPLL_PWR_CTRL			SCI_ADDR(REGS_PMU_APB_BASE, 0x032C)/*GPLL_PWR_CTRL*/
#define REG_PMU_APB_WTLCP_SYS_WAKEUP_IRQ_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x0330)/*WTLCP_SYS_WAKEUP_IRQ_EN*/
#define REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY	SCI_ADDR(REGS_PMU_APB_BASE, 0x0334)/*PD_CA53_LIT_MP4_SHUTDOWN_DLY*/
#define REG_PMU_APB_AON_MEM_CTRL			SCI_ADDR(REGS_PMU_APB_BASE, 0x033C)/*AON_MEM_CTRL*/
#define REG_PMU_APB_PAD_OUT_ADIE_CTRL1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0340)/*PAD_OUT_ADIE_CTRL1*/
#define REG_PMU_APB_PD_WAIT_CNT1			SCI_ADDR(REGS_PMU_APB_BASE, 0x344)/*PD_WAIT_CNT1*/
#define REG_PMU_APB_PD_WAIT_CNT2			SCI_ADDR(REGS_PMU_APB_BASE, 0x348)/*PD_WAIT_CNT2*/
#define REG_PMU_APB_LVDS_RF_PLL_REF_SEL			SCI_ADDR(REGS_PMU_APB_BASE, 0x34C)/*LVDS_RF_PLL_REF_SEL*/
#define REG_PMU_APB_PAD_CFG_EN_ANLGMODE			SCI_ADDR(REGS_PMU_APB_BASE, 0x0500)/*PAD_CFG_EN_ANLGMODE*/
#define REG_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3000)/*PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3004)/*PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3008)/*PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x300C)/*PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3010)/*PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3014)/*PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3018)/*PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x301C)/*PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3020)/*PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3024)/*PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3028)/*PD_CA53_TOP_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x302C)/*PD_AP_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3030)/*PD_GPU_TOP_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3034)/*PD_GPU_C0_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3038)/*PD_GPU_C1_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_VSP_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x303c)/*PD_VSP_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_CAM_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3040)/*PD_CAM_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_DISP_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3044)/*PD_DISP_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_PUB0_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3048)/*PD_PUB0_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_PUB1_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x304c)/*PD_PUB1_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3050)/*PD_WTLCP_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_TGDSP_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3054)/*PD_WTLCP_TGDSP_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_LDSP_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3058)/*PD_WTLCP_LDSP_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x305c)/*PD_WTLCP_HU3GE_B_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3060)/*PD_WTLCP_HU3GE_A_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_GSM_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3064)/*PD_WTLCP_GSM_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_TD_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3068)/*PD_WTLCP_TD_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_LTE_P1_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x306c)/*PD_WTLCP_LTE_P1_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_LTE_P2_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3070)/*PD_WTLCP_LTE_P2_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_AGCP_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3074)/*PD_AGCP_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_AGCP_DSP_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3078)/*PD_AGCP_DSP_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_AGCP_GSM_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x307c)/*PD_AGCP_GSM_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_PUBCP_SYS_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3080)/*PD_PUBCP_SYS_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_DDR0_ACC_RDY			SCI_ADDR(REGS_PMU_APB_BASE, 0x3084)/*DDR0_ACC_RDY*/
#define REG_PMU_APB_DDR1_ACC_RDY			SCI_ADDR(REGS_PMU_APB_BASE, 0x3088)/*DDR1_ACC_RDY*/
#define REG_PMU_APB_DDR0_LIGHT_ACC_RDY_B		SCI_ADDR(REGS_PMU_APB_BASE, 0x308C)/*DDR0_LIGHT_SLEEP_RDY_B*/
#define REG_PMU_APB_DDR1_LIGHT_ACC_RDY_B		SCI_ADDR(REGS_PMU_APB_BASE, 0x3090)/*DDR1_LIGHT_SLEEP_RDY_B*/
#define REG_PMU_APB_PD_WTLCP_LTE_P3_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3094)/*PD_WTLCP_LTE_P3_SHUTDOWN_MARK_STATUS*/
#define REG_PMU_APB_PD_WTLCP_LTE_P4_SHUTDOWN_MARK_STATUS	SCI_ADDR(REGS_PMU_APB_BASE, 0x3098)/*PD_WTLCP_LTE_P4_SHUTDOWN_MARK_STATUS*/



/* bits definitions for register REG_PMU_APB_PD_CA53_TOP_CFG */
#define BIT_PMU_APB_PD_CA53_TOP_DBG_SHUTDOWN_EN			( BIT(28) )
#define BIT_PMU_APB_PD_CA53_TOP_PD_SEL				( BIT(27) )
#define BIT_PMU_APB_PD_CA53_TOP_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_CA53_TOP_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_TOP_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_TOP_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_TOP_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_CFG */
#define BIT_PMU_APB_PD_CA53_LIT_MP4_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C0_CFG */
#define BIT_PMU_APB_PD_CA53_LIT_C0_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_LIT_C0_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C1_CFG */
#define BIT_PMU_APB_PD_CA53_LIT_C1_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_LIT_C1_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C2_CFG */
#define BIT_PMU_APB_PD_CA53_LIT_C2_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_LIT_C2_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C3_CFG */
#define BIT_PMU_APB_PD_CA53_LIT_C3_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_LIT_C3_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_MP4_CFG */
#define BIT_PMU_APB_PD_CA53_BIG_MP4_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C0_CFG */
#define BIT_PMU_APB_PD_CA53_BIG_C0_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_BIG_C0_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C1_CFG */
#define BIT_PMU_APB_PD_CA53_BIG_C1_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_BIG_C1_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C2_CFG */
#define BIT_PMU_APB_PD_CA53_BIG_C2_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_BIG_C2_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C3_CFG */
#define BIT_PMU_APB_PD_CA53_BIG_C3_DBG_SHUTDOWN_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_CA53_BIG_C3_WAKEUP_EN			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
#define BIT_PMU_APB_PD_AP_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_AP_SYS_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_AP_SYS_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_AP_SYS_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_VSP_SYS_CFG */
#define BIT_PMU_APB_PD_VSP_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_VSP_SYS_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_VSP_SYS_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_VSP_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_VSP_SYS_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_DBG_SYS_CFG */
#define BIT_PMU_APB_PD_DBG_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_DBG_SYS_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_DBG_SYS_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_DBG_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_DBG_SYS_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_CAM_SYS_CFG */
#define BIT_PMU_APB_PD_CAM_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_CAM_SYS_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_CAM_SYS_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_CAM_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_CAM_SYS_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_DISP_SYS_CFG */
#define BIT_PMU_APB_PD_DISP_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_DISP_SYS_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_DISP_SYS_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_DISP_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_DISP_SYS_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
#define BIT_PMU_APB_PD_GPU_TOP_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_GPU_TOP_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_GPU_TOP_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_GPU_TOP_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_GPU_C0_CFG */
#define BIT_PMU_APB_PD_GPU_C0_RST_N_MASK			( BIT(26) )
#define BIT_PMU_APB_PD_GPU_C0_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_GPU_C0_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_GPU_C0_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_GPU_C0_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_GPU_C0_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_GPU_C1_CFG */
#define BIT_PMU_APB_PD_GPU_C1_RST_N_MASK			( BIT(26) )
#define BIT_PMU_APB_PD_GPU_C1_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_GPU_C1_AUTO_SHUTDOWN_EN			( BIT(24) )
#define BIT_PMU_APB_PD_GPU_C1_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_GPU_C1_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_GPU_C1_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_PUB0_SYS_CFG */
#define BIT_PMU_APB_PD_PUB0_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_PUB0_SYS_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_PUB0_SYS_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_PUB0_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_PUB0_SYS_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_PUB1_SYS_CFG */
#define BIT_PMU_APB_PD_PUB1_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_PUB1_SYS_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_PUB1_SYS_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_PUB1_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_PUB1_SYS_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_SYS_CFG */
#define BIT_PMU_APB_PD_WTLCP_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_SYS_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_SYS_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_SYS_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_TGDSP_CFG */
#define BIT_PMU_APB_PD_WTLCP_TGDSP_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LDSP_CFG */
#define BIT_PMU_APB_PD_WTLCP_LDSP_PD_SEL			( BIT(27) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_HU3GE_A_CFG */
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_GSM_CFG */
#define BIT_PMU_APB_PD_WTLCP_GSM_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_GSM_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_GSM_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_GSM_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_GSM_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_TD_CFG */
#define BIT_PMU_APB_PD_WTLCP_TD_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_TD_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_TD_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_TD_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_TD_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P1_CFG */
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P2_CFG */
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_AGCP_SYS_CFG */
#define BIT_PMU_APB_PD_AGCP_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_AGCP_SYS_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_AGCP_SYS_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_AGCP_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_AGCP_SYS_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_AGCP_DSP_CFG */
#define BIT_PMU_APB_PD_AGCP_DSP_PD_SEL				( BIT(27) )
#define BIT_PMU_APB_PD_AGCP_DSP_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_AGCP_DSP_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_AGCP_DSP_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_AGCP_DSP_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_AGCP_DSP_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_AGCP_GSM_CFG */
#define BIT_PMU_APB_PD_AGCP_GSM_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_AGCP_GSM_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_AGCP_GSM_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_AGCP_GSM_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_AGCP_GSM_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_PUBCP_SYS_CFG */
#define BIT_PMU_APB_PD_PUBCP_DBG_SHUTDOWN_EN			( BIT(26) )
#define BIT_PMU_APB_PD_PUBCP_SYS_FORCE_SHUTDOWN			( BIT(25) )
#define BIT_PMU_APB_PD_PUBCP_SYS_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_PUBCP_SYS_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_PUBCP_SYS_PWR_ON_SEQ_DLY(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_PUBCP_SYS_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_RC_WAIT_CNT */
#define BIT_PMU_APB_RC0_WAIT_CNT(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_RC1_WAIT_CNT(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
#define BIT_PMU_APB_XTL0_WAIT_CNT(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )

/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
#define BIT_PMU_APB_XTLBUF2_WAIT_CNT(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_XTLBUF1_WAIT_CNT(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_XTLBUF0_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
#define BIT_PMU_APB_DPLL1_WAIT_CNT(_X_)			( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_PMU_APB_DPLL0_WAIT_CNT(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_MPLL1_WAIT_CNT(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_MPLL0_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
#define BIT_PMU_APB_LTEPLL1_WAIT_CNT(_X_)			( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_PMU_APB_LTEPLL_WAIT_CNT(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_TWPLL_WAIT_CNT(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_LVDSDIS_PLL_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT3 */
#define BIT_PMU_APB_GPLL_WAIT_CNT(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_RPLL1_WAIT_CNT(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_RPLL0_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_AP_LP_AUTO_CTRL */
#define BIT_PMU_APB_GPU_CA53_CCI_EN				( BIT(6) )
#define BIT_PMU_APB_DAP_CA53_CCI_EN				( BIT(5) )
#define BIT_PMU_APB_CA53_LIT_AUTO_CLK_CTRL_DISABLE		( BIT(4) )
#define BIT_PMU_APB_CA53_BIG_AUTO_CLK_CTRL_DISABLE		( BIT(3) )
#define BIT_PMU_APB_CA53_CCI_LP_CTRL_DISABLE			( BIT(2) )
#define BIT_PMU_APB_CA53_NIU_LP_CTRL_DISABLE			( BIT(1) )
#define BIT_PMU_APB_CA53_NIC_LP_CTRL_DISABLE			( BIT(0) )

/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
#define BIT_PMU_APB_XTLBUF0_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_XTLBUF0_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_XTLBUF0_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_XTLBUF0_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_XTLBUF0_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_XTLBUF0_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
#define BIT_PMU_APB_XTL0_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_XTL0_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_XTL0_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_XTL0_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_XTL0_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_XTL0_AP_SEL					( BIT(2) )

/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
#define BIT_PMU_APB_MPLL1_RELOCK_EN				( BIT(23) )
#define BIT_PMU_APB_MPLL1_CM3_SEL				( BIT(22) )
#define BIT_PMU_APB_MPLL1_AGCP_SEL				( BIT(21) )
#define BIT_PMU_APB_MPLL1_WTLCP_SEL				( BIT(20) )
#define BIT_PMU_APB_MPLL1_PUBCP_SEL				( BIT(19) )
#define BIT_PMU_APB_MPLL1_AP_SEL				( BIT(18) )
#define BIT_PMU_APB_MPLL0_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_MPLL0_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_MPLL0_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_MPLL0_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_MPLL0_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_MPLL0_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
#define BIT_PMU_APB_DPLL1_RELOCK_EN				( BIT(23) )
#define BIT_PMU_APB_DPLL1_CM3_SEL				( BIT(22) )
#define BIT_PMU_APB_DPLL1_AGCP_SEL				( BIT(21) )
#define BIT_PMU_APB_DPLL1_WTLCP_SEL				( BIT(20) )
#define BIT_PMU_APB_DPLL1_PUBCP_SEL				( BIT(19) )
#define BIT_PMU_APB_DPLL1_AP_SEL				( BIT(18) )
#define BIT_PMU_APB_DPLL0_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_DPLL0_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_DPLL0_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_DPLL0_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_DPLL0_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_DPLL0_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */
#define BIT_PMU_APB_LTEPLL_RELOCK_EN				( BIT(10) )
#define BIT_PMU_APB_LTEPLL_REF_SEL(_X_)			( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_LTEPLL_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_LTEPLL_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_LTEPLL_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_LTEPLL_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_LTEPLL_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */
#define BIT_PMU_APB_TWPLL_RELOCK_EN				( BIT(10) )
#define BIT_PMU_APB_TWPLL_REF_SEL(_X_)				( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_TWPLL_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_TWPLL_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_TWPLL_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_TWPLL_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_TWPLL_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */
#define BIT_PMU_APB_LVDSDIS_PLL_RELOCK_EN			( BIT(7) )
#define BIT_PMU_APB_LVDSDIS_PLL_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_LVDSDIS_PLL_AGCP_SEL			( BIT(5) )
#define BIT_PMU_APB_LVDSDIS_PLL_WTLCP_SEL			( BIT(4) )
#define BIT_PMU_APB_LVDSDIS_PLL_PUBCP_SEL			( BIT(3) )
#define BIT_PMU_APB_LVDSDIS_PLL_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_SYS_SOFT_RST */
#define BIT_PMU_APB_WTLCP_DSP_SYS_SOFT_RST			( BIT(31) )
#define BIT_PMU_APB_WCDMA_AON_SOFT_RST				( BIT(30) )
#define BIT_PMU_APB_AGCP_AON_SOFT_RST				( BIT(29) )
#define BIT_PMU_APB_AGCP_SOFT_RST				( BIT(28) )
#define BIT_PMU_APB_WTLCP_SOFT_RST				( BIT(27) )
#define BIT_PMU_APB_DBG_SOFT_RST				( BIT(23) )
#define BIT_PMU_APB_WTLCP_AON_SOFT_RST				( BIT(22) )
#define BIT_PMU_APB_CM3_SOFT_RST				( BIT(21) )
#define BIT_PMU_APB_PUB1_SOFT_RST				( BIT(20) )
#define BIT_PMU_APB_PUB0_SOFT_RST				( BIT(19) )
#define BIT_PMU_APB_AP_SOFT_RST					( BIT(18) )
#define BIT_PMU_APB_CA53_TOP_SOFT_RST				( BIT(17) )
#define BIT_PMU_APB_GPU_SOFT_RST				( BIT(6) )
#define BIT_PMU_APB_DISP_SOFT_RST				( BIT(5) )
#define BIT_PMU_APB_CAM_SOFT_RST				( BIT(4) )
#define BIT_PMU_APB_VSP_SOFT_RST				( BIT(3) )
#define BIT_PMU_APB_PUBCP_SOFT_RST				( BIT(2) )
#define BIT_PMU_APB_CM3_CORE_SOFT_RST				( BIT(1) )

/* bits definitions for register REG_PMU_APB_PUBCP_SLP_STATUS_DBG0 */
#define BIT_PMU_APB_PUBCP_DEEP_SLP_DBG(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_WTLCP_SLP_STATUS_DBG0 */
#define BIT_PMU_APB_WTLCP_DEEP_SLP_DBG(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_AGCP_SLP_STATUS_DBG0 */
#define BIT_PMU_APB_AGCP_DEEP_SLP_DBG(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
#define BIT_PMU_APB_PD_WTLCP_SYS_STATE(_X_)			( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_STATE(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_STATE(_X_)		( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_STATE(_X_)			( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_STATE(_X_)			( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_PD_CA53_TOP_STATE(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
#define BIT_PMU_APB_PD_CA53_BIG_C1_STATE(_X_)			( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_STATE(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_STATE(_X_)			( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_STATE(_X_)			( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_STATE(_X_)			( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_STATE(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
#define BIT_PMU_APB_PD_WTLCP_LDSP_STATE(_X_)			( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_STATE(_X_)		( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_PMU_APB_PD_WTLCP_GSM_STATE(_X_)			( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BIT_PMU_APB_PD_WTLCP_TD_STATE(_X_)			( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_STATE(_X_)			( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_STATE(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
#define BIT_PMU_APB_PD_AGCP_SYS_STATE(_X_)			( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BIT_PMU_APB_PD_AGCP_DSP_STATE(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_PMU_APB_PD_AGCP_GSM_STATE(_X_)			( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BIT_PMU_APB_PD_PUBCP_SYS_STATE(_X_)			( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BIT_PMU_APB_PD_PUB0_SYS_STATE(_X_)			( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_PD_PUB1_SYS_STATE(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_PMU_APB_PWR_STATUS4_DBG */
#define BIT_PMU_APB_PD_CA53_BIG_C3_STATE(_X_)			( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_STATE(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_PMU_APB_PD_AP_SYS_STATE(_X_)			( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BIT_PMU_APB_PD_DISP_SYS_STATE(_X_)			( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BIT_PMU_APB_PD_CAM_SYS_STATE(_X_)			( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_PD_VSP_SYS_STATE(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
#define BIT_PMU_APB_CA53_TOP_FORCE_LIGHT_SLEEP			( BIT(29) )
#define BIT_PMU_APB_AGCP_FORCE_LIGHT_SLEEP			( BIT(28) )
#define BIT_PMU_APB_WTLCP_FORCE_LIGHT_SLEEP			( BIT(27) )
#define BIT_PMU_APB_PUBCP_FORCE_LIGHT_SLEEP			( BIT(26) )
#define BIT_PMU_APB_AP_FORCE_LIGHT_SLEEP			( BIT(25) )
#define BIT_PMU_APB_CM3_FORCE_DEEP_SLEEP			( BIT(23) )
#define BIT_PMU_APB_AGCP_FORCE_DEEP_SLEEP			( BIT(21) )
#define BIT_PMU_APB_WTLCP_FORCE_DEEP_SLEEP			( BIT(20) )
#define BIT_PMU_APB_PUBCP_FORCE_DEEP_SLEEP			( BIT(19) )
#define BIT_PMU_APB_AP_FORCE_DEEP_SLEEP				( BIT(18) )
#define BIT_PMU_APB_AGCP_LIGHT_SLEEP				( BIT(12) )
#define BIT_PMU_APB_WTLCP_LIGHT_SLEEP				( BIT(11) )
#define BIT_PMU_APB_PUBCP_LIGHT_SLEEP				( BIT(10) )
#define BIT_PMU_APB_AP_LIGHT_SLEEP				( BIT(9) )
#define BIT_PMU_APB_AGCP_DEEP_SLEEP				( BIT(4) )
#define BIT_PMU_APB_WTLCP_DEEP_SLEEP				( BIT(3) )
#define BIT_PMU_APB_PUBCP_DEEP_SLEEP				( BIT(2) )
#define BIT_PMU_APB_AP_DEEP_SLEEP				( BIT(1) )
#define BIT_PMU_APB_CM3_DEEP_SLEEP				( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
#define BIT_PMU_APB_DDR1_PHY_SOFT_RST				( BIT(24) )
#define BIT_PMU_APB_DDR1_AHB_SOFT_RST				( BIT(23) )
#define BIT_PMU_APB_DDR1_PHY_AUTO_GATE_EN			( BIT(22) )
#define BIT_PMU_APB_DDR1_UMCTL_SOFT_RST				( BIT(21) )
#define BIT_PMU_APB_DDR1_UMCTL_AUTO_GATE_EN			( BIT(20) )
#define BIT_PMU_APB_DDR1_PHY_EB					( BIT(18) )
#define BIT_PMU_APB_DDR1_UMCTL_EB				( BIT(17) )
#define BIT_PMU_APB_DDR0_PHY_SOFT_RST				( BIT(8) )
#define BIT_PMU_APB_DDR0_AHB_SOFT_RST				( BIT(7) )
#define BIT_PMU_APB_DDR0_PHY_AUTO_GATE_EN			( BIT(6) )
#define BIT_PMU_APB_DDR0_UMCTL_SOFT_RST				( BIT(5) )
#define BIT_PMU_APB_DDR0_UMCTL_AUTO_GATE_EN			( BIT(4) )
#define BIT_PMU_APB_DDR0_PHY_EB					( BIT(2) )
#define BIT_PMU_APB_DDR0_UMCTL_EB				( BIT(1) )

/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
#define BIT_PMU_APB_CM3_SLP_STATUS(_X_)			( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BIT_PMU_APB_AGCP_SLP_STATUS(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_WTLCP_SLP_STATUS(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BIT_PMU_APB_PUBCP_SLP_STATUS(_X_)			( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_AP_SLP_STATUS(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_DDR0_CHN_SLEEP_CTRL0 */
#define BIT_PMU_APB_DDR0_CTRL_CGM_SEL				( BIT(30) )
#define BIT_PMU_APB_DDR0_CHN9_CGM_SEL				( BIT(9) )
#define BIT_PMU_APB_DDR0_CHN8_CGM_SEL				( BIT(8) )
#define BIT_PMU_APB_DDR0_CHN7_CGM_SEL				( BIT(7) )
#define BIT_PMU_APB_DDR0_CHN6_CGM_SEL				( BIT(6) )
#define BIT_PMU_APB_DDR0_CHN5_CGM_SEL				( BIT(5) )
#define BIT_PMU_APB_DDR0_CHN4_CGM_SEL				( BIT(4) )
#define BIT_PMU_APB_DDR0_CHN3_CGM_SEL				( BIT(3) )
#define BIT_PMU_APB_DDR0_CHN2_CGM_SEL				( BIT(2) )
#define BIT_PMU_APB_DDR0_CHN1_CGM_SEL				( BIT(1) )
#define BIT_PMU_APB_DDR0_CHN0_CGM_SEL				( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR1_CHN_SLEEP_CTRL0 */
#define BIT_PMU_APB_DDR1_CTRL_CGM_SEL				( BIT(30) )
#define BIT_PMU_APB_DDR1_CHN9_CGM_SEL				( BIT(9) )
#define BIT_PMU_APB_DDR1_CHN8_CGM_SEL				( BIT(8) )
#define BIT_PMU_APB_DDR1_CHN7_CGM_SEL				( BIT(7) )
#define BIT_PMU_APB_DDR1_CHN6_CGM_SEL				( BIT(6) )
#define BIT_PMU_APB_DDR1_CHN5_CGM_SEL				( BIT(5) )
#define BIT_PMU_APB_DDR1_CHN4_CGM_SEL				( BIT(4) )
#define BIT_PMU_APB_DDR1_CHN3_CGM_SEL				( BIT(3) )
#define BIT_PMU_APB_DDR1_CHN2_CGM_SEL				( BIT(2) )
#define BIT_PMU_APB_DDR1_CHN1_CGM_SEL				( BIT(1) )
#define BIT_PMU_APB_DDR1_CHN0_CGM_SEL				( BIT(0) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P3_CFG */
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P4_CFG */
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
#define BIT_PMU_APB_XTLBUF1_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_XTLBUF1_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_XTLBUF1_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_XTLBUF1_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_XTLBUF1_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_XTLBUF1_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_XTLBUF2_REL_CFG */
#define BIT_PMU_APB_XTLBUF2_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_XTLBUF2_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_XTLBUF2_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_XTLBUF2_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_XTLBUF2_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_XTLBUF2_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_LTEPLL1_REL_CFG */
#define BIT_PMU_APB_LTEPLL1_RELOCK_EN				( BIT(10) )
#define BIT_PMU_APB_LTEPLL1_REF_SEL(_X_)			( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_LTEPLL1_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_LTEPLL1_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_LTEPLL1_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_LTEPLL1_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_LTEPLL1_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
#define BIT_PMU_APB_AON_RC_4M_SEL				( BIT(8) )
#define BIT_PMU_APB_PUB1_26M_SEL				( BIT(6) )
#define BIT_PMU_APB_PUB0_26M_SEL				( BIT(5) )
#define BIT_PMU_APB_AON_26M_SEL					( BIT(4) )
#define BIT_PMU_APB_AGCP_26M_SEL				( BIT(3) )
#define BIT_PMU_APB_WTLCP_26M_SEL				( BIT(2) )
#define BIT_PMU_APB_PUBCP_26M_SEL				( BIT(1) )
#define BIT_PMU_APB_AP_26M_SEL					( BIT(0) )

/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS1 */
#define BIT_PMU_APB_PD_GPU_SYS_BISR_DONE			( BIT(31) )
#define BIT_PMU_APB_PD_CA53_TOP_BISR_DONE			( BIT(30) )
#define BIT_PMU_APB_PD_GPU_C1_BISR_DONE				( BIT(29) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_BISR_DONE			( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_BISR_DONE			( BIT(27) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_BISR_DONE			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_BISR_DONE			( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_BISR_DONE			( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_BISR_DONE			( BIT(23) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_BISR_DONE			( BIT(22) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_BISR_DONE			( BIT(21) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_BISR_DONE			( BIT(20) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_BISR_DONE			( BIT(19) )
#define BIT_PMU_APB_PD_AP_SYS_BISR_DONE				( BIT(18) )
#define BIT_PMU_APB_PD_DISP_SYS_BISR_DONE			( BIT(17) )
#define BIT_PMU_APB_PD_CAM_SYS_BISR_DONE			( BIT(16) )
#define BIT_PMU_APB_PD_VSP_SYS_BISR_DONE			( BIT(15) )
#define BIT_PMU_APB_PD_DBG_SYS_BISR_DONE			( BIT(14) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_BISR_DONE			( BIT(13) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_BISR_DONE			( BIT(12) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_BISR_DONE			( BIT(11) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_BISR_DONE			( BIT(10) )
#define BIT_PMU_APB_PD_WTLCP_TD_BISR_DONE			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_BISR_DONE			( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_BISR_DONE			( BIT(7) )
#define BIT_PMU_APB_PD_WTLCP_GSM_BISR_DONE			( BIT(6) )
#define BIT_PMU_APB_PD_WTLCP_SYS_BISR_DONE			( BIT(5) )
#define BIT_PMU_APB_PD_GPU_C0_BISR_DONE				( BIT(4) )
#define BIT_PMU_APB_PD_PUBCP_SYS_BISR_DONE			( BIT(3) )
#define BIT_PMU_APB_PD_AGCP_GSM_BISR_DONE			( BIT(2) )
#define BIT_PMU_APB_PD_AGCP_DSP_BISR_DONE			( BIT(1) )
#define BIT_PMU_APB_PD_AGCP_SYS_BISR_DONE			( BIT(0) )

/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS1 */
#define BIT_PMU_APB_PD_GPU_SYS_BISR_BUSY			( BIT(31) )
#define BIT_PMU_APB_PD_CA53_TOP_BISR_BUSY			( BIT(30) )
#define BIT_PMU_APB_PD_GPU_C1_BISR_BUSY				( BIT(29) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_BISR_BUSY			( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_BISR_BUSY			( BIT(27) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_BISR_BUSY			( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_BISR_BUSY			( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_BISR_BUSY			( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_BISR_BUSY			( BIT(23) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_BISR_BUSY			( BIT(22) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_BISR_BUSY			( BIT(21) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_BISR_BUSY			( BIT(20) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_BISR_BUSY			( BIT(19) )
#define BIT_PMU_APB_PD_AP_SYS_BISR_BUSY				( BIT(18) )
#define BIT_PMU_APB_PD_DISP_SYS_BISR_BUSY			( BIT(17) )
#define BIT_PMU_APB_PD_CAM_SYS_BISR_BUSY			( BIT(16) )
#define BIT_PMU_APB_PD_VSP_SYS_BISR_BUSY			( BIT(15) )
#define BIT_PMU_APB_PD_DBG_SYS_BISR_BUSY			( BIT(14) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_BISR_BUSY			( BIT(13) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_BISR_BUSY			( BIT(12) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_BISR_BUSY			( BIT(11) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_BISR_BUSY			( BIT(10) )
#define BIT_PMU_APB_PD_WTLCP_TD_BISR_BUSY			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_BISR_BUSY			( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_BISR_BUSY			( BIT(7) )
#define BIT_PMU_APB_PD_WTLCP_GSM_BISR_BUSY			( BIT(6) )
#define BIT_PMU_APB_PD_WTLCP_SYS_BISR_BUSY			( BIT(5) )
#define BIT_PMU_APB_PD_GPU_C0_BISR_BUSY				( BIT(4) )
#define BIT_PMU_APB_PD_PUBCP_SYS_BISR_BUSY			( BIT(3) )
#define BIT_PMU_APB_PD_AGCP_GSM_BISR_BUSY			( BIT(2) )
#define BIT_PMU_APB_PD_AGCP_DSP_BISR_BUSY			( BIT(1) )
#define BIT_PMU_APB_PD_AGCP_SYS_BISR_BUSY			( BIT(0) )

/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG1 */
#define BIT_PMU_APB_PD_GPU_SYS_BISR_FORCE_BYP			( BIT(31) )
#define BIT_PMU_APB_PD_CA53_TOP_BISR_FORCE_BYP			( BIT(30) )
#define BIT_PMU_APB_PD_GPU_C1_BISR_FORCE_BYP			( BIT(29) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_BISR_FORCE_BYP		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_BISR_FORCE_BYP		( BIT(27) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_BISR_FORCE_BYP		( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_BISR_FORCE_BYP		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_BISR_FORCE_BYP		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_BISR_FORCE_BYP		( BIT(23) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_BISR_FORCE_BYP		( BIT(22) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_BISR_FORCE_BYP		( BIT(21) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_BISR_FORCE_BYP		( BIT(20) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_BISR_FORCE_BYP		( BIT(19) )
#define BIT_PMU_APB_PD_AP_SYS_BISR_FORCE_BYP			( BIT(18) )
#define BIT_PMU_APB_PD_DISP_SYS_BISR_FORCE_BYP			( BIT(17) )
#define BIT_PMU_APB_PD_CAM_SYS_BISR_FORCE_BYP			( BIT(16) )
#define BIT_PMU_APB_PD_VSP_SYS_BISR_FORCE_BYP			( BIT(15) )
#define BIT_PMU_APB_PD_DBG_SYS_BISR_FORCE_BYP			( BIT(14) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_BISR_FORCE_BYP		( BIT(13) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_BISR_FORCE_BYP		( BIT(12) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_BISR_FORCE_BYP		( BIT(11) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_BISR_FORCE_BYP		( BIT(10) )
#define BIT_PMU_APB_PD_WTLCP_TD_BISR_FORCE_BYP			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_BISR_FORCE_BYP		( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_BISR_FORCE_BYP		( BIT(7) )
#define BIT_PMU_APB_PD_WTLCP_GSM_BISR_FORCE_BYP			( BIT(6) )
#define BIT_PMU_APB_PD_WTLCP_SYS_BISR_FORCE_BYP			( BIT(5) )
#define BIT_PMU_APB_PD_GPU_C0_BISR_FORCE_BYP			( BIT(4) )
#define BIT_PMU_APB_PD_PUBCP_SYS_BISR_FORCE_BYP			( BIT(3) )
#define BIT_PMU_APB_PD_AGCP_GSM_BISR_FORCE_BYP			( BIT(2) )
#define BIT_PMU_APB_PD_AGCP_DSP_BISR_FORCE_BYP			( BIT(1) )
#define BIT_PMU_APB_PD_AGCP_SYS_BISR_FORCE_BYP			( BIT(0) )

/* bits definitions for register REG_PMU_APB_BISR_EN_CFG1 */
#define BIT_PMU_APB_PD_GPU_SYS_BISR_FORCE_EN			( BIT(31) )
#define BIT_PMU_APB_PD_CA53_TOP_BISR_FORCE_EN			( BIT(30) )
#define BIT_PMU_APB_PD_GPU_C1_BISR_FORCE_EN			( BIT(29) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_BISR_FORCE_EN		( BIT(28) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_BISR_FORCE_EN		( BIT(27) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_BISR_FORCE_EN		( BIT(26) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_BISR_FORCE_EN		( BIT(25) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_BISR_FORCE_EN		( BIT(24) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_BISR_FORCE_EN		( BIT(23) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_BISR_FORCE_EN		( BIT(22) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_BISR_FORCE_EN		( BIT(21) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_BISR_FORCE_EN		( BIT(20) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_BISR_FORCE_EN		( BIT(19) )
#define BIT_PMU_APB_PD_DBG_SYS_BISR_FORCE_EN			( BIT(18) )
#define BIT_PMU_APB_PD_AP_SYS_BISR_FORCE_EN			( BIT(17) )
#define BIT_PMU_APB_PD_DISP_SYS_BISR_FORCE_EN			( BIT(16) )
#define BIT_PMU_APB_PD_CAM_SYS_BISR_FORCE_EN			( BIT(15) )
#define BIT_PMU_APB_PD_VSP_SYS_BISR_FORCE_EN			( BIT(14) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_BISR_FORCE_EN		( BIT(13) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_BISR_FORCE_EN			( BIT(12) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_BISR_FORCE_EN		( BIT(11) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_BISR_FORCE_EN		( BIT(10) )
#define BIT_PMU_APB_PD_WTLCP_TD_BISR_FORCE_EN			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_BISR_FORCE_EN		( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_BISR_FORCE_EN		( BIT(7) )
#define BIT_PMU_APB_PD_WTLCP_GSM_BISR_FORCE_EN			( BIT(6) )
#define BIT_PMU_APB_PD_WTLCP_SYS_BISR_FORCE_EN			( BIT(5) )
#define BIT_PMU_APB_PD_GPU_C0_BISR_FORCE_EN			( BIT(4) )
#define BIT_PMU_APB_PD_PUBCP_SYS_BISR_FORCE_EN			( BIT(3) )
#define BIT_PMU_APB_PD_AGCP_GSM_BISR_FORCE_EN			( BIT(2) )
#define BIT_PMU_APB_PD_AGCP_DSP_BISR_FORCE_EN			( BIT(1) )
#define BIT_PMU_APB_PD_AGCP_SYS_BISR_FORCE_EN			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */
#define BIT_PMU_APB_CGM_AUTO_GATE_SEL_CFG0(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */
#define BIT_PMU_APB_CGM_AUTO_GATE_SEL_CFG1(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */
#define BIT_PMU_APB_CGM_AUTO_GATE_SEL_CFG2(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */
#define BIT_PMU_APB_CGM_AUTO_GATE_SEL_CFG3(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */
#define BIT_PMU_APB_CGM_FORCE_EN_CFG0(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */
#define BIT_PMU_APB_CGM_FORCE_EN_CFG1(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */
#define BIT_PMU_APB_CGM_FORCE_EN_CFG2(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */
#define BIT_PMU_APB_CGM_FORCE_EN_CFG3(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */
#define BIT_PMU_APB_CM3_SLEEP_XTL_ON				( BIT(6) )
#define BIT_PMU_APB_AGCP_SLEEP_XTL_ON				( BIT(5) )
#define BIT_PMU_APB_WTLCP_SLEEP_XTL_ON				( BIT(4) )
#define BIT_PMU_APB_PUBCP_SLEEP_XTL_ON				( BIT(3) )
#define BIT_PMU_APB_AP_SLEEP_XTL_ON				( BIT(0) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_HU3GE_B_CFG */
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_FORCE_SHUTDOWN		( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_AUTO_SHUTDOWN_EN		( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_PWR_ON_DLY(_X_)		( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_PWR_ON_SEQ_DLY(_X_)	( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_ISO_ON_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG0 */
#define BIT_PMU_APB_MEM_SLP_CFG0(_X_)				(_X_)

/* bits definitions for register REG_PMU_APB_MEM_SD_CFG0 */
#define BIT_PMU_APB_MEM_SD_CFG0(_X_)				(_X_)

/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_EN */
#define BIT_PMU_APB_MEM_AUTO_SLP_EN(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_EN */
#define BIT_PMU_APB_MEM_AUTO_SD_EN(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS2 */
#define BIT_PMU_APB_PD_PUB0_SYS_BISR_DONE			( BIT(10) )
#define BIT_PMU_APB_PD_PUB1_SYS_BISR_DONE			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_BISR_DONE			( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_BISR_DONE			( BIT(7) )

/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS2 */
#define BIT_PMU_APB_PD_PUB0_SYS_BISR_BUSY			( BIT(10) )
#define BIT_PMU_APB_PD_PUB1_SYS_BISR_BUSY			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_BISR_BUSY			( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_BISR_BUSY			( BIT(7) )

/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG2 */
#define BIT_PMU_APB_PD_PUB0_SYS_BISR_FORCE_BYP			( BIT(10) )
#define BIT_PMU_APB_PD_PUB1_SYS_BISR_FORCE_BYP			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_BISR_FORCE_BYP		( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_BISR_FORCE_BYP		( BIT(7) )

/* bits definitions for register REG_PMU_APB_BISR_EN_CFG2 */
#define BIT_PMU_APB_PD_PUB0_SYS_BISR_FORCE_EN			( BIT(10) )
#define BIT_PMU_APB_PD_PUB1_SYS_BISR_FORCE_EN			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_BISR_FORCE_EN		( BIT(8) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_BISR_FORCE_EN		( BIT(7) )

/* bits definitions for register REG_PMU_APB_RPLL_REL_CFG */
#define BIT_PMU_APB_RPLL1_RELOCK_EN				( BIT(23) )
#define BIT_PMU_APB_RPLL1_CM3_SEL				( BIT(22) )
#define BIT_PMU_APB_RPLL1_AGCP_SEL				( BIT(21) )
#define BIT_PMU_APB_RPLL1_WTLCP_SEL				( BIT(20) )
#define BIT_PMU_APB_RPLL1_PUBCP_SEL				( BIT(19) )
#define BIT_PMU_APB_RPLL1_AP_SEL				( BIT(18) )
#define BIT_PMU_APB_RPLL0_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_RPLL0_CM3_SEL				( BIT(6) )
#define BIT_PMU_APB_RPLL0_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_RPLL0_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_RPLL0_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_RPLL0_AP_SEL				( BIT(2) )

/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */
#define BIT_PMU_APB_PUBCP_PWR_WAIT_CNT(_X_)			( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_PMU_APB_AGCP_PWR_WAIT_CNT(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_WTLCP_PWR_WAIT_CNT(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_AP_PWR_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */
#define BIT_PMU_APB_SLP_CTRL_CLK_DIV_CFG(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)) )
#define BIT_PMU_APB_CM3_PWR_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_RC_REL_CFG */
#define BIT_PMU_APB_RC1_RELOCK_EN				( BIT(14) )
#define BIT_PMU_APB_RC1_CM3_SEL					( BIT(13) )
#define BIT_PMU_APB_RC1_AGCP_SEL				( BIT(12) )
#define BIT_PMU_APB_RC1_WTLCP_SEL				( BIT(11) )
#define BIT_PMU_APB_RC1_PUBCP_SEL				( BIT(10) )
#define BIT_PMU_APB_RC1_AP_SEL					( BIT(9) )
#define BIT_PMU_APB_RC0_RELOCK_EN				( BIT(7) )
#define BIT_PMU_APB_RC0_CM3_SEL					( BIT(6) )
#define BIT_PMU_APB_RC0_AGCP_SEL				( BIT(5) )
#define BIT_PMU_APB_RC0_WTLCP_SEL				( BIT(4) )
#define BIT_PMU_APB_RC0_PUBCP_SEL				( BIT(3) )
#define BIT_PMU_APB_RC0_AP_SEL					( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR_SLEEP_DISABLE_ACK_BYP */
#define BIT_PMU_APB_DPLL1_GLB_CGM_EN_BYP			( BIT(5) )
#define BIT_PMU_APB_DPLL0_GLB_CGM_EN_BYP			( BIT(4) )
#define BIT_PMU_APB_DDR1_GLB_CGM_EN_BYP				( BIT(3) )
#define BIT_PMU_APB_DDR0_GLB_CGM_EN_BYP				( BIT(2) )
#define BIT_PMU_APB_DDR1_SLEEP_DISABLE_ACK_BYP			( BIT(1) )
#define BIT_PMU_APB_DDR0_SLEEP_DISABLE_ACK_BYP			( BIT(0) )

/* bits definitions for register REG_PMU_APB_GLB_SLEEP_ENABLE */
#define BIT_PMU_APB_DDR1_GLB_LIGHT_SLEEP_ENABLE			( BIT(3) )
#define BIT_PMU_APB_DDR1_GLB_DEEP_SLEEP_ENABLE			( BIT(2) )
#define BIT_PMU_APB_DDR0_GLB_LIGHT_SLEEP_ENABLE			( BIT(1) )
#define BIT_PMU_APB_DDR0_GLB_DEEP_SLEEP_ENABLE			( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR_SLEEP_DISABLE_ACK */
#define BIT_PMU_APB_DDR1_GLB_CGM_EN				( BIT(3) )
#define BIT_PMU_APB_DDR0_GLB_CGM_EN				( BIT(2) )
#define BIT_PMU_APB_DDR1_SLEEP_DISABLE_ACK			( BIT(1) )
#define BIT_PMU_APB_DDR0_SLEEP_DISABLE_ACK			( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR_SLEEP_DISABLE */
#define BIT_PMU_APB_DDR1_SLEEP_DISABLE				( BIT(1) )
#define BIT_PMU_APB_DDR0_SLEEP_DISABLE				( BIT(0) )

/* bits definitions for register REG_PMU_APB_PUB_FORCE_SLEEP */
#define BIT_PMU_APB_PUB0_FORCE_LIGHT_SLEEP			( BIT(3) )
#define BIT_PMU_APB_PUB1_FORCE_LIGHT_SLEEP			( BIT(2) )
#define BIT_PMU_APB_PUB1_FORCE_DEEP_SLEEP			( BIT(1) )
#define BIT_PMU_APB_PUB0_FORCE_DEEP_SLEEP			( BIT(0) )

/* bits definitions for register REG_PMU_APB_NOC_SLEEP_STOP_BYP */
#define BIT_PMU_APB_CA53_TOP_NOC_LIGHT_SLEEP_STOP_BYP		( BIT(19) )
#define BIT_PMU_APB_AGCP_SYS_NOC_LIGHT_SLEEP_STOP_BYP		( BIT(15) )
#define BIT_PMU_APB_WTLCP_SYS_NOC_LIGHT_SLEEP_STOP_BYP		( BIT(14) )
#define BIT_PMU_APB_PUBCP_SYS_NOC_LIGHT_SLEEP_STOP_BYP		( BIT(13) )
#define BIT_PMU_APB_AP_SYS_NOC_LIGHT_SLEEP_STOP_BYP		( BIT(10) )
#define BIT_PMU_APB_CA53_TOP_NOC_SLEEP_STOP_BYP			( BIT(9) )
#define BIT_PMU_APB_DISP_SYS_NOC_SLEEP_STOP_BYP			( BIT(8) )
#define BIT_PMU_APB_CAM_SYS_NOC_SLEEP_STOP_BYP			( BIT(7) )
#define BIT_PMU_APB_VSP_SYS_NOC_SLEEP_STOP_BYP			( BIT(6) )
#define BIT_PMU_APB_AGCP_SYS_NOC_SLEEP_STOP_BYP			( BIT(5) )
#define BIT_PMU_APB_WTLCP_SYS_NOC_SLEEP_STOP_BYP		( BIT(4) )
#define BIT_PMU_APB_PUBCP_SYS_NOC_SLEEP_STOP_BYP		( BIT(3) )
#define BIT_PMU_APB_PUB1_SYS_NOC_SLEEP_STOP_BYP			( BIT(2) )
#define BIT_PMU_APB_PUB0_SYS_NOC_SLEEP_STOP_BYP			( BIT(1) )
#define BIT_PMU_APB_AP_SYS_NOC_SLEEP_STOP_BYP			( BIT(0) )

/* bits definitions for register REG_PMU_APB_NOC_SLEEP_STOP_STATUS */
#define BIT_PMU_APB_CA53_TOP_NOC_SLEEP_STOP			( BIT(9) )
#define BIT_PMU_APB_DISP_SYS_NOC_SLEEP_STOP			( BIT(8) )
#define BIT_PMU_APB_CAM_SYS_NOC_SLEEP_STOP			( BIT(7) )
#define BIT_PMU_APB_VSP_SYS_NOC_SLEEP_STOP			( BIT(6) )
#define BIT_PMU_APB_AGCP_SYS_NOC_SLEEP_STOP			( BIT(5) )
#define BIT_PMU_APB_WTLCP_SYS_NOC_SLEEP_STOP			( BIT(4) )
#define BIT_PMU_APB_PUBCP_SYS_NOC_SLEEP_STOP			( BIT(3) )
#define BIT_PMU_APB_PUB1_SYS_NOC_SLEEP_STOP			( BIT(2) )
#define BIT_PMU_APB_PUB0_SYS_NOC_SLEEP_STOP			( BIT(1) )
#define BIT_PMU_APB_AP_SYS_NOC_SLEEP_STOP			( BIT(0) )

/* bits definitions for register REG_PMU_APB_AGCP_DSP_CORE_INT_DISABLE */
#define BIT_PMU_APB_AGCP_DSP_CORE_INT_DISABLE			( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_TGDSP_CORE_INT_DISABLE */
#define BIT_PMU_APB_WTLCP_TGDSP_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_LDSP_CORE_INT_DISABLE */
#define BIT_PMU_APB_WTLCP_LDSP_CORE_INT_DISABLE			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C0_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_LIT_C0_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C1_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_LIT_C1_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C2_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_LIT_C2_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C3_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_LIT_C3_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C0_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_BIG_C0_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C1_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_BIG_C1_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C2_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_BIG_C2_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C3_CORE_INT_DISABLE */
#define BIT_PMU_APB_CA53_BIG_C3_CORE_INT_DISABLE		( BIT(0) )

/* bits definitions for register REG_PMU_APB_PUBCP_CR5_CORE_INT_DISABLE */
#define BIT_PMU_APB_PUBCP_CR5_CORE_INT_DISABLE			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC0 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC0(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SEL */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_SOFT			( BIT(1) )
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SEL			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC1 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC1(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC2 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC2(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC3 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC3(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC4 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC4(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC5 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_TEST_SRC5(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_TEST_SRC */
#define BIT_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_TEST_SRC(_X_)	(_X_)

/* bits definitions for register REG_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_TEST_SEL */
#define BIT_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_SOFT			( BIT(1) )
#define BIT_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_TEST_SEL		( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_TEST_SRC */
#define BIT_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_TEST_SRC(_X_)	(_X_)

/* bits definitions for register REG_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_TEST_SEL */
#define BIT_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_SOFT			( BIT(1) )
#define BIT_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_TEST_SEL		( BIT(0) )

/* bits definitions for register REG_PMU_APB_AGCP_DSP_WAKEUP_IRQ_TEST_SRC */
#define BIT_PMU_APB_AGCP_DSP_WAKEUP_IRQ_TEST_SRC(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_AGCP_DSP_WAKEUP_IRQ_TEST_SEL */
#define BIT_PMU_APB_AGCP_DSP_WAKEUP_IRQ_SOFT			( BIT(1) )
#define BIT_PMU_APB_AGCP_DSP_WAKEUP_IRQ_TEST_SEL		( BIT(0) )

/* bits definitions for register REG_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_TEST_SRC */
#define BIT_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_TEST_SRC(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_TEST_SEL */
#define BIT_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_SOFT			( BIT(1) )
#define BIT_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_TEST_SEL		( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_EN0 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_EN0(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_EN1 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_EN1(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_EN2 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_EN2(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_EN3 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_EN3(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_EN4 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_EN4(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_CA53_WAKEUP_IRQ_EN5 */
#define BIT_PMU_APB_CA53_WAKEUP_IRQ_EN5(_X_)			(_X_)

/* bits definitions for register REG_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_EN */
#define BIT_PMU_APB_WTLCP_TGDSP_WAKEUP_IRQ_EN(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_AGCP_DSP_WAKEUP_IRQ_EN */
#define BIT_PMU_APB_AGCP_DSP_WAKEUP_IRQ_EN(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_EN */
#define BIT_PMU_APB_PUBCP_CR5_WAKEUP_IRQ_EN(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_EN */
#define BIT_PMU_APB_WTLCP_LDSP_WAKEUP_IRQ_EN(_X_)		(_X_)

/* bits definitions for register REG_PMU_APB_CM3_DSLP_ENA */
#define BIT_PMU_APB_CM3_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C3_DSLP_ENA */
#define BIT_PMU_APB_CA53_BIG_C3_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C2_DSLP_ENA */
#define BIT_PMU_APB_CA53_BIG_C2_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C1_DSLP_ENA */
#define BIT_PMU_APB_CA53_BIG_C1_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_C0_DSLP_ENA */
#define BIT_PMU_APB_CA53_BIG_C0_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C3_DSLP_ENA */
#define BIT_PMU_APB_CA53_LIT_C3_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C2_DSLP_ENA */
#define BIT_PMU_APB_CA53_LIT_C2_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C1_DSLP_ENA */
#define BIT_PMU_APB_CA53_LIT_C1_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_C0_DSLP_ENA */
#define BIT_PMU_APB_CA53_LIT_C0_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_TGDSP_DSLP_ENA */
#define BIT_PMU_APB_WTLCP_TGDSP_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_LDSP_DSLP_ENA */
#define BIT_PMU_APB_WTLCP_LDSP_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_AGCP_DSP_DSLP_ENA */
#define BIT_PMU_APB_AGCP_DSP_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_BIG_MP4_DSLP_ENA */
#define BIT_PMU_APB_CA53_BIG_MP4_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_LIT_MP4_DSLP_ENA */
#define BIT_PMU_APB_CA53_LIT_MP4_DSLP_ENA			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CA53_TOP_DSLP_ENA */
#define BIT_PMU_APB_CA53_TOP_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_AP_DSLP_ENA */
#define BIT_PMU_APB_AP_DSLP_ENA					( BIT(0) )

/* bits definitions for register REG_PMU_APB_PUBCP_DSLP_ENA */
#define BIT_PMU_APB_PUBCP_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_DSLP_ENA */
#define BIT_PMU_APB_WTLCP_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_AGCP_DSLP_ENA */
#define BIT_PMU_APB_AGCP_DSLP_ENA				( BIT(0) )

/* bits definitions for register REG_PMU_APB_USB_PMU */
#define BIT_PMU_APB_USB_PMU_ACK_BYP				( BIT(3) )
#define BIT_PMU_APB_USB_PMU_REQUEST(_X_)			( (_X_) << 1 & (BIT(1)|BIT(2)) )

/* bits definitions for register REG_PMU_APB_PWR_STATUS6_DBG */
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_STATE(_X_)			( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_STATE(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_PMU_APB_PWR_ST_DEBUG_DLY0 */
#define BIT_PMU_APB_CGM_OFF_DLY(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_PMU_APB_CGM_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_ISO_OFF_DLY(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_RST_DEASSERT_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PWR_ST_DEBUG_DLY1 */
#define BIT_PMU_APB_SHUTDOWN_M_D_DLY(_X_)			( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BIT_PMU_APB_PWR_ST_CLK_DIV_CFG(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)) )
#define BIT_PMU_APB_RST_ASSERT_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_LIGHT_SLEEP_ENABLE */
#define BIT_PMU_APB_AGCP_LSLP_ENA				( BIT(3) )
#define BIT_PMU_APB_WTLCP_LSLP_ENA				( BIT(2) )
#define BIT_PMU_APB_PUBCP_LSLP_ENA				( BIT(1) )
#define BIT_PMU_APB_AP_LSLP_ENA					( BIT(0) )

/* bits definitions for register REG_PMU_APB_PAD_OUT_ADIE_CTRL0 */
#define BIT_PMU_APB_PAD_OUT_XTL_EB_DISP_EB_MASK			( BIT(31) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_DISP_EB_MASK		( BIT(30) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_GPU_SHUTDOWN_MASK		( BIT(29) )
#define BIT_PMU_APB_PAD_OUT_DCDC_CA53_BIG_EB_POL_SEL		( BIT(28) )
#define BIT_PMU_APB_PAD_OUT_DCDC_CA53_LIT_EB_POL_SEL		( BIT(27) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_POL_SEL			( BIT(26) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_POL_SEL			( BIT(25) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_POL_SEL			( BIT(24) )
#define BIT_PMU_APB_PAD_OUT_DCDC_CA53_BIG_FRC_ON		( BIT(23) )
#define BIT_PMU_APB_PAD_OUT_DCDC_CA53_LIT_FRC_ON		( BIT(22) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_EXT_XTL_PD_MASK		( BIT(21) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_CM3_DEEP_SLEEP_MASK	( BIT(20) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_AGCP_DEEP_SLEEP_MASK	( BIT(19) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_WTLCP_DEEP_SLEEP_MASK	( BIT(18) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_PUBCP_DEEP_SLEEP_MASK	( BIT(17) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_AP_DEEP_SLEEP_MASK	( BIT(16) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_EXT_XTL_PD_MASK		( BIT(15) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_CM3_DEEP_SLEEP_MASK		( BIT(14) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_AGCP_DEEP_SLEEP_MASK		( BIT(13) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_WTLCP_DEEP_SLEEP_MASK	( BIT(12) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_PUBCP_DEEP_SLEEP_MASK	( BIT(11) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB_AP_DEEP_SLEEP_MASK		( BIT(10) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_EXT_XTL_PD_MASK		( BIT(9) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_CM3_DEEP_SLEEP_MASK	( BIT(8) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_AGCP_DEEP_SLEEP_MASK	( BIT(7) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_WTLCP_DEEP_SLEEP_MASK	( BIT(6) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_PUBCP_DEEP_SLEEP_MASK	( BIT(5) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_AP_DEEP_SLEEP_MASK	( BIT(4) )
#define BIT_PMU_APB_EXT_XTL3_COMB_EN				( BIT(3) )
#define BIT_PMU_APB_EXT_XTL2_COMB_EN				( BIT(2) )
#define BIT_PMU_APB_EXT_XTL1_COMB_EN				( BIT(1) )
#define BIT_PMU_APB_EXT_XTL0_COMB_EN				( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR_PHY_DATA_FRC_RET */
#define BIT_PMU_APB_DDR1_PHY_DATA_AUTO_RET_EN			( BIT(3) )
#define BIT_PMU_APB_DDR0_PHY_DATA_AUTO_RET_EN			( BIT(2) )
#define BIT_PMU_APB_DDR1_PHY_DATA_FRC_RET			( BIT(1) )
#define BIT_PMU_APB_DDR0_PHY_DATA_FRC_RET			( BIT(0) )

/* bits definitions for register REG_PMU_APB_PLL_CNT_DONE_STATUS */
#define BIT_PMU_APB_LTEPLL1_CNT_DONE				( BIT(16) )
#define BIT_PMU_APB_XTLBUF2_CNT_DONE				( BIT(15) )
#define BIT_PMU_APB_GPLL_CNT_DONE				( BIT(14) )
#define BIT_PMU_APB_XTLBUF1_CNT_DONE				( BIT(13) )
#define BIT_PMU_APB_XTL0_CNT_DONE				( BIT(12) )
#define BIT_PMU_APB_LVDSDIS_PLL_CNT_DONE			( BIT(11) )
#define BIT_PMU_APB_LTEPLL_CNT_DONE				( BIT(10) )
#define BIT_PMU_APB_TWPLL_CNT_DONE				( BIT(9) )
#define BIT_PMU_APB_DPLL1_CNT_DONE				( BIT(8) )
#define BIT_PMU_APB_DPLL0_CNT_DONE				( BIT(7) )
#define BIT_PMU_APB_RPLL1_CNT_DONE				( BIT(6) )
#define BIT_PMU_APB_RPLL0_CNT_DONE				( BIT(5) )
#define BIT_PMU_APB_MPLL1_CNT_DONE				( BIT(4) )
#define BIT_PMU_APB_MPLL0_CNT_DONE				( BIT(3) )
#define BIT_PMU_APB_RC1_CNT_DONE				( BIT(2) )
#define BIT_PMU_APB_RC0_CNT_DONE				( BIT(1) )
#define BIT_PMU_APB_XTLBUF0_CNT_DONE				( BIT(0) )

/* bits definitions for register REG_PMU_APB_POWER_SWITCH_ACK_D_STATUS0 */
#define BIT_PMU_APB_PD_PUBCP_SYS_ACK_D				( BIT(31) )
#define BIT_PMU_APB_PD_AGCP_GSM_ACK_D				( BIT(30) )
#define BIT_PMU_APB_PD_AGCP_DSP_ACK_D				( BIT(29) )
#define BIT_PMU_APB_PD_AGCP_SYS_ACK_D				( BIT(28) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_ACK_D			( BIT(27) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_ACK_D			( BIT(26) )
#define BIT_PMU_APB_PD_WTLCP_TD_ACK_D				( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_GSM_ACK_D				( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_WCDMA_ACK_D			( BIT(23) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_ACK_D				( BIT(22) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_ACK_D			( BIT(21) )
#define BIT_PMU_APB_PD_WTLCP_SYS_ACK_D				( BIT(20) )
#define BIT_PMU_APB_PD_PUB1_SYS_ACK_D				( BIT(19) )
#define BIT_PMU_APB_PD_PUB0_SYS_ACK_D				( BIT(18) )
#define BIT_PMU_APB_PD_GPU_C1_ACK_D				( BIT(17) )
#define BIT_PMU_APB_PD_GPU_C0_ACK_D				( BIT(16) )
#define BIT_PMU_APB_PD_GPU_TOP_ACK_D				( BIT(15) )
#define BIT_PMU_APB_PD_DISP_SYS_ACK_D				( BIT(14) )
#define BIT_PMU_APB_PD_CAM_SYS_ACK_D				( BIT(13) )
#define BIT_PMU_APB_PD_VSP_SYS_ACK_D				( BIT(12) )
#define BIT_PMU_APB_PD_AP_SYS_ACK_D				( BIT(11) )
#define BIT_PMU_APB_PD_CA53_TOP_ACK_D				( BIT(10) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_ACK_D			( BIT(9) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_ACK_D			( BIT(8) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_ACK_D			( BIT(7) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_ACK_D			( BIT(6) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_ACK_D			( BIT(5) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_ACK_D			( BIT(4) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_ACK_D			( BIT(3) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_ACK_D			( BIT(2) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_ACK_D			( BIT(1) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_ACK_D			( BIT(0) )

/* bits definitions for register REG_PMU_APB_POWER_SWITCH_ACK_M_STATUS0 */
#define BIT_PMU_APB_PD_PUBCP_SYS_ACK_M				( BIT(31) )
#define BIT_PMU_APB_PD_AGCP_GSM_ACK_M				( BIT(30) )
#define BIT_PMU_APB_PD_AGCP_DSP_ACK_M				( BIT(29) )
#define BIT_PMU_APB_PD_AGCP_SYS_ACK_M				( BIT(28) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_ACK_M			( BIT(27) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_ACK_M			( BIT(26) )
#define BIT_PMU_APB_PD_WTLCP_TD_ACK_M				( BIT(25) )
#define BIT_PMU_APB_PD_WTLCP_GSM_ACK_M				( BIT(24) )
#define BIT_PMU_APB_PD_WTLCP_WCDMA_ACK_M			( BIT(23) )
#define BIT_PMU_APB_PD_WTLCP_LDSP_ACK_M				( BIT(22) )
#define BIT_PMU_APB_PD_WTLCP_TGDSP_ACK_M			( BIT(21) )
#define BIT_PMU_APB_PD_WTLCP_SYS_ACK_M				( BIT(20) )
#define BIT_PMU_APB_PD_PUB1_SYS_ACK_M				( BIT(19) )
#define BIT_PMU_APB_PD_PUB0_SYS_ACK_M				( BIT(18) )
#define BIT_PMU_APB_PD_GPU_C1_ACK_M				( BIT(17) )
#define BIT_PMU_APB_PD_GPU_C0_ACK_M				( BIT(16) )
#define BIT_PMU_APB_PD_GPU_TOP_ACK_M				( BIT(15) )
#define BIT_PMU_APB_PD_DISP_SYS_ACK_M				( BIT(14) )
#define BIT_PMU_APB_PD_CAM_SYS_ACK_M				( BIT(13) )
#define BIT_PMU_APB_PD_VSP_SYS_ACK_M				( BIT(12) )
#define BIT_PMU_APB_PD_AP_SYS_ACK_M				( BIT(11) )
#define BIT_PMU_APB_PD_CA53_TOP_ACK_M				( BIT(10) )
#define BIT_PMU_APB_PD_CA53_BIG_MP4_ACK_M			( BIT(9) )
#define BIT_PMU_APB_PD_CA53_BIG_C3_ACK_M			( BIT(8) )
#define BIT_PMU_APB_PD_CA53_BIG_C2_ACK_M			( BIT(7) )
#define BIT_PMU_APB_PD_CA53_BIG_C1_ACK_M			( BIT(6) )
#define BIT_PMU_APB_PD_CA53_BIG_C0_ACK_M			( BIT(5) )
#define BIT_PMU_APB_PD_CA53_LIT_MP4_ACK_M			( BIT(4) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_ACK_M			( BIT(3) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_ACK_M			( BIT(2) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_ACK_M			( BIT(1) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_ACK_M			( BIT(0) )

/* bits definitions for register REG_PMU_APB_POWER_SWITCH_ACK_D_STATUS1 */
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_ACK_D			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_ACK_D			( BIT(8) )
#define BIT_PMU_APB_PD_DBG_SYS_ACK_D				( BIT(7) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_ACK_D			( BIT(6) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_ACK_D			( BIT(5) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_L1RAM_ACK_D			( BIT(4) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_L1RAM_ACK_D			( BIT(3) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_L1RAM_ACK_D			( BIT(2) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_L1RAM_ACK_D			( BIT(1) )
#define BIT_PMU_APB_PD_CA53_LIT_L2RAM_ACK_D			( BIT(0) )

/* bits definitions for register REG_PMU_APB_POWER_SWITCH_ACK_M_STATUS1 */
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_ACK_M			( BIT(9) )
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_ACK_M			( BIT(8) )
#define BIT_PMU_APB_PD_DBG_SYS_ACK_M				( BIT(7) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_ACK_M			( BIT(6) )
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_ACK_M			( BIT(5) )
#define BIT_PMU_APB_PD_CA53_LIT_C3_L1RAM_ACK_M			( BIT(4) )
#define BIT_PMU_APB_PD_CA53_LIT_C2_L1RAM_ACK_M			( BIT(3) )
#define BIT_PMU_APB_PD_CA53_LIT_C1_L1RAM_ACK_M			( BIT(2) )
#define BIT_PMU_APB_PD_CA53_LIT_C0_L1RAM_ACK_M			( BIT(1) )
#define BIT_PMU_APB_PD_CA53_LIT_L2RAM_ACK_M			( BIT(0) )

/* bits definitions for register REG_PMU_APB_CGM_PMU_SEL */
#define BIT_PMU_APB_CGM_PMU_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )

/* bits definitions for register REG_PMU_APB_GPLL_PWR_CTRL */
#define BIT_PMU_APB_GPLL_PD					( BIT(0) )

/* bits definitions for register REG_PMU_APB_WTLCP_SYS_WAKEUP_IRQ_EN */
#define BIT_PMU_APB_WTLCP_SYS_WAKEUP_IRQ_EN			( BIT(0) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY */
#define BIT_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_DLY(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_AON_MEM_CTRL */
#define BIT_PMU_APB_CM3_MEM_ALL_SLEEP_EN			( BIT(1) )
#define BIT_PMU_APB_AON_MEM_CM3_SLEEP_EN			( BIT(0) )

/* bits definitions for register REG_PMU_APB_PAD_OUT_ADIE_CTRL1 */
#define BIT_PMU_APB_PAD_OUT_XTL_EB_PLL_PD_MASK			( BIT(23) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_PLL_PD_MASK		( BIT(22) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_PLL_PD_MASK			( BIT(21) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_PLL_PD_MASK			( BIT(20) )
#define BIT_PMU_APB_PAD_OUT_CHIP_SLEEP_PLL_PD_MASK		( BIT(19) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_POL_SEL			( BIT(18) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_POL_SEL			( BIT(17) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_DISP_EB_MASK		( BIT(16) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_GPU_SHUTDOWN_MASK		( BIT(15) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_EXT_XTL_PD_MASK		( BIT(14) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_CM3_DEEP_SLEEP_MASK		( BIT(13) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_AGCP_DEEP_SLEEP_MASK	( BIT(12) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_WTLCP_DEEP_SLEEP_MASK	( BIT(11) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_PUBCP_DEEP_SLEEP_MASK	( BIT(10) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB2_AP_DEEP_SLEEP_MASK		( BIT(9) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_DISP_EB_MASK		( BIT(8) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_GPU_SHUTDOWN_MASK		( BIT(7) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_EXT_XTL_PD_MASK		( BIT(6) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_CM3_DEEP_SLEEP_MASK		( BIT(5) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_AGCP_DEEP_SLEEP_MASK	( BIT(4) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_WTLCP_DEEP_SLEEP_MASK	( BIT(3) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_PUBCP_DEEP_SLEEP_MASK	( BIT(2) )
#define BIT_PMU_APB_PAD_OUT_XTL_EB1_AP_DEEP_SLEEP_MASK		( BIT(1) )
#define BIT_PMU_APB_DCXO_LC_DEEP_SLEEP_DISP_EB_MASK		( BIT(0) )

/* bits definitions for register REG_PMU_APB_PD_WAIT_CNT1 */
#define BIT_PMU_APB_PUBCP_PWR_PD_WAIT_CNT(_X_)			( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_PMU_APB_AGCP_PWR_PD_WAIT_CNT(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BIT_PMU_APB_WTLCP_PWR_PD_WAIT_CNT(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_PMU_APB_AP_PWR_PD_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_PD_WAIT_CNT2 */
#define BIT_PMU_APB_CM3_PWR_PD_WAIT_CNT(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_PMU_APB_LVDS_RF_PLL_REF_SEL */
#define BIT_PMU_APB_LVDS_RF_PLL1_REF_SEL(_X_)			( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BIT_PMU_APB_LVDS_RF_PLL0_REF_SEL(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_PMU_APB_PAD_CFG_EN_ANLGMODE */
#define BIT_PMU_APB_PAD_CFG_EN_ANLGMODE				( BIT(0) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_VSP_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_VSP_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_CAM_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_CAM_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_DISP_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_DISP_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_PUB0_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_PUB0_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_PUB1_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_PUB1_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_TGDSP_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_TGDSP_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LDSP_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_LDSP_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_HU3GE_B_SHUTDOWN_MARK(_X_)	( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_HU3GE_A_SHUTDOWN_MARK(_X_)	( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_GSM_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_GSM_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_TD_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_TD_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P1_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_LTE_P1_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P2_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_LTE_P2_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_AGCP_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_AGCP_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_AGCP_DSP_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_AGCP_DSP_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_AGCP_GSM_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_AGCP_GSM_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_PUBCP_SYS_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_PUBCP_SYS_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_DDR0_ACC_RDY */
#define BIT_PMU_APB_DDR0_ACC_RDY				( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR1_ACC_RDY */
#define BIT_PMU_APB_DDR1_ACC_RDY				( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR0_LIGHT_ACC_RDY_B */
#define BIT_PMU_APB_DDR0_LIGHT_ACC_RDY				( BIT(0) )

/* bits definitions for register REG_PMU_APB_DDR1_LIGHT_ACC_RDY_B */
#define BIT_PMU_APB_DDR1_LIGHT_ACC_RDY				( BIT(0) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P3_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_LTE_P3_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )

/* bits definitions for register REG_PMU_APB_PD_WTLCP_LTE_P4_SHUTDOWN_MARK_STATUS */
#define BIT_PMU_APB_PD_WTLCP_LTE_P4_SHUTDOWN_MARK(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
#endif
